• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The inventive method is used to control a single-phase DC / AC converter, wherein in the operation of the converter, an electric power is transmitted from a DC side to an AC side or vice versa and thereby in successive half oscillations one with a fundamental frequency at the AC Side occurring sinusoidal AC voltage (u0) each during a first time interval of the half-wave, which extends over a substantial portion of the half-oscillation, a first converter stage (1, 2) generates an intermediate voltage (uC1) with a sinusoidal half-wave, and the AC voltage (u0) is generated by adding the intermediate voltage (uC1) to a reference voltage (uC2) substantially constant during the first time interval, or by switching the polarity of each successive sinusoidal half-wave of the intermediate voltage (uC1). In each case during a second time interval, which has no overlap with the first time interval, a voltage setpoint (uC1 *) for the intermediate voltage (uC1) is limited downwards to a lower limit value. The invention also relates to a device for controlling a single-phase DC / AC converter.
    公开号:CH711423A2
    申请号:CH01139/15
    申请日:2015-08-06
    公开日:2017-02-15
    发明作者:Bortis Dominik；Krismer Florian；Lobsiger Yannik；Neumayr Dominik；Walter Kolar Johann
    申请人:ETH Zürich；
    IPC主号:
    专利说明:

    [0001] The invention relates to the field of power electronic converters or converters, and more particularly to a method and apparatus for controlling a single phase DC / AC converter.
    With regard to power flow bidirectional single-stage coupling of a DC voltage source (hereinafter DC source) to a single-phase AC power network (hereinafter referred to as AC network), or the generation of an AC (power) voltage from a DC voltage (in difference for coupling to a given mains voltage referred to as "isolated operation") takes place in the simplest case by a hybrid-modulated full bridge circuit (inverter circuit) which two, arranged by the positive against the negative DC terminal bridge arms, ie a first and a second bridge branch each having two power transistors in series (an upper and a lower transistor) with antiparallel freewheeling diodes. At the exit of the first bridge branch, i. At the junction between the transistors can then by alternately turning on the upper and lower transistor (the other transistor remains locked), based on the negative rail of the DC input voltage, a pulse width modulated square wave voltage waveform with positive voltage blocks in the amount of DC input voltage and intermediate sections are generated with zero voltage; With an appropriate choice of the relative turn-on of the transistors is thus a course of the local (relative to a pulse period) mean value of the bridge branch output voltage a form of a power-frequency sinusoidal semi-vibration adjustable. If the output of the first bridge branch is then connected to a first terminal of the network via an output inductance and the second network terminal is connected directly to the output of the second bridge branch, and the second bridge branch with mains frequency is switched at the zero crossing of the AC voltage, so that the second network terminal during the positive mains voltage half-wave with the negative and subsequently, while the negative mains voltage half-wave is connected to the positive DC voltage rail, so that a supply of power from the DC source into the AC grid is possible. The different timing of the two bridge branches of the system (switching frequency pulse width modulation and power frequency switching) justified the term as a hybrid modulated AC / DC converter.
    Within a positive mains voltage half-wave (physically positive pointing from the first to the second network terminal) so the lower transistor of the second bridge branch is permanently turned on and with the first bridge branch by pulse width modulation (slightly) over the mains voltage sinusoidal (consideration of the local, on set voltage average value) corresponding amplitude and phase position, or by the then occurring across the output inductance voltage difference in the output inductance, imprinted in the sense of minimizing reactive power advantageous sinusoidal, lying in phase to the mains voltage current or fed into the network. However, due to pulse width modulation, the output current has a switching frequency ripple superimposed on the sinusoidal waveform which is advantageously provided by a filter capacitance located between the power terminals (or alternatively applied by the first power terminal against the positive and / or negative DC voltage bills) which converts the output inductance to one Low-pass filter added, kept away from the mains. Within the negative network half-cycle, the upper transistor of the second bridge branch is turned on (and the lower transistor is off), i. the second network terminal permanently connected to the positive DC voltage rail and by means of the first bridge branch a corresponding, again one (slightly) exceeds the mains voltage negative sine half-wave against the positive voltage rail generated and so a negative current half-wave impressed by the output inductance. The power frequency clocking bridge branch thus clearly fulfills a rectifier function, since it ultimately allows to form from the time varying, but compared to the negative DC rail always positive output voltage of the high-frequency clocking first bridge branch at the output of the full bridge, an AC voltage for the feed an AC current is needed in the grid.
    Since only one bridge branch is operated at high frequency, the switching losses are halved compared to an always simultaneous high-frequency clocking of both bridge branches or is given a higher efficiency of energy conversion; Furthermore, the control and regulation of the converter with respect to a simultaneous high-frequency clocking of the two bridge arms less complexity.
    The, on the basis of the preceding description (topology and timing) generally as single-stage hybrid modulated single-phase DC / AC converter circuit to be designated due to the anti-parallel to the switches lying diodes not only as (bidirectional) inverter (feeding a current general phase position in the network) but also as a rectifier (current consumption from the grid) work. If then only a sinusoidal current consumption in phase with the mains voltage, i. only unidirectional power flow or no formation of net reactive power required, the transistors of the low-frequency clocking bridge branch can be omitted; the remaining diodes then take over the switching of the output of the second bridge branch as a function of the mains voltage polarity or line current direction due to their unidirectionality.
    However, the bidirectional, as well as the unidirectional system is limited in terms of ensuring a sinusoidal current waveform in the vicinity of the mains voltage zero crossings. Approaches, e.g. the mains voltage within the positive half-oscillation is zero, there is hardly any counter voltage (mains voltage) available for the reduction of the positive current fed into the network (positively counted from the output of the first bridge branch in the direction of the network); Therefore, there is a current distortion, which leads to low-frequency harmonics of the mains current and limits the usability of the circuit in demand for very low network perturbations.
    This effect is also given for an alternative, two-stage version of the hybrid modulated DC / AC converter, which also has a high-frequency operated and a power-frequency clocking circuit part. It is there again a transistor full bridge circuit arranged (the transistors again have antiparallel freewheeling diodes), the bridge branch outputs directly (i.A., via an EMC filter, which, however, has no significant longitudinal impedance for mains frequency operations) are connected to the power terminals. The switching of the full bridge is done at mains frequency, with two diagonally opposite transistors are always in the through state, ie within the positive power half voltage of the upper transistor of the left and the lower transistor of the right bridge branch is turned on and locked at zero crossing to the negative half-wave these two transistors and the other two transistors (the lower transistor of the left and the upper transistor of the right bridge branch) are switched through. The applied between the output of the left and the output of the right bridge branch (and positively counted in this direction network voltage) is thus switched once directly and once with inverse polarity to the DC side of the transistor full bridge circuit, which there related to the lower DC Terminal of the full bridge the rectified mains voltage occurs. Thus, the rectifier function is implemented, but there is still no possibility of a sinusoidal current injection. Therefore, between the positive and negative terminals of the DC source, there is another converter stage, i. a bridge circuit with output inductance is continuously high frequency clocked, and the end of the output inductance facing away from the bridge branch is applied to the upper terminal of the transistor full bridge circuit and the lower terminal of the bridge branch is connected to the negative terminal of the DC source and the lower DC terminal of the full bridge. By selecting the turn-on and turn-off of the transistors of the high-frequency clocking bridge branch, then, based on the negative DC terminal, a voltage can be formed such that a current predetermined course pressed into the upper terminal of the transistor full bridge circuit and thus ultimately via the Ausgangsinduktivität is fed into the grid. In order to avoid a forwarding of the switching-frequency ripple of the current in the output inductance, a filter capacitance is advantageously arranged between the upper and lower DC terminal of the transistor full-bridge circuit, which forms an LC low-pass filter together with the output inductance. A circuit of completely the same basic structure can also be used for supplying energy from the AC network to a DC voltage source (charging). The transistors of the full bridge can then be omitted, i. only diodes or only one diode full bridge circuit can be provided. The current in the output inductance is then proportional to the rectified mains voltage by clocking the high-frequency operated half-bridge and physically impressed from the upper terminal of the transistor full-bridge circuit in the direction of the DC voltage source, whereby the AC side is ideally sinusoidal, in phase with the mains voltage lying current results. This circuit is also known as a single phase Power Factor Corrected (PFC) rectifier.
    However, regardless of the actual implementation of the system in the vicinity of the zero crossings of the mains voltage, current distortion again occurs, i. E. a deviation of the current of the desired sinusoidal shape, since then there is only a small voltage between the upper and lower terminal of the full bridge circuit, or for a reduction of the current in the Ausgangsinduktivität with switched lower transistor of the high frequency clocking bridge branch hardly more voltage available stands. The thus limited current controllability becomes particularly clear when, in addition to active power, reactive power is also to be fed into the network (as is increasingly required, for example, for photovoltaic inverters). The zero crossing of the mains current is then shifted from the zero crossing of the mains voltage, or flows before switching the full bridge in the voltage zero crossing in the upper output terminal of the full bridge, a non-zero current, which changed during the switching by appropriate control of the high-frequency clocking bridge branch to the inverse value must be in order to ensure a smooth current flow on the AC side (ideal), despite the inversion of the switching state of the transistor full bridge. The reversal of the current flow direction in the output inductance, however, can take place only relatively slowly in the absence of reverse voltage, resulting in a relatively strong distortion of the mains current, or relatively high network perturbations occur.
    The object of the invention is therefore, methods or associated control devices for operation hybrid modulated, i. to provide a (essentially) switching frequency and a power-frequency clocked circuit part existing single-phase AC / DC converter, which ensure regardless of the phase shift of the mains and mains voltage in the vicinity of the voltage zero crossings a sinusoidal line current profile or avoid system perturbations.
    To achieve this object, a method and apparatus for controlling a single-phase DC / AC converter with the features of the corresponding independent claims.
    The method is used to control a single-phase DC / AC converter, wherein in the operation of the converter, an electric power from a DC (DC) side to an AC (AC) side or vice versa is transmitted, and in successive half-cycles a sinusoidal AC voltage occurring at a fundamental frequency on the AC side each during a first time interval of the half-wave extending over a substantial portion of the half-wave, a first converter stage generating an intermediate voltage having a sinusoidal half-wave, and the AC voltageby adding (of successive sinusoidal half-waves) the intermediate voltage to a reference voltage substantially constant during the first time interval, respectively, oris generated by switching the polarity of each successive sinusoidal half-wave oscillations of the intermediate voltage.
    In each case, during a second time interval which has no overlap with the first time interval, a voltage setpoint for the intermediate voltage is limited down to a lower limit.
    By limiting the intermediate voltage and not going to zero, it can be used to regulate current into the load or source at an AC-side reactive load or source.
    The switching of the polarity of each successive sinusoidal half oscillations of the intermediate voltage is done twice per period, that is twice the fundamental frequency.
    The first time interval lasts for example at least 70% or 80% or 90% or 95% of the duration of a half-oscillation. The second time interval is in each case about a zero crossing of the AC voltage and lasts for example at least 5% or 10% or 20% or 30% of the duration of a half-oscillation.
    Typically, the first and second time intervals follow each other alternately and without gaps.
    In other words, therefore, the low-frequency clocking circuit part becomes temporary, i. E. operated in the vicinity of the mains voltage zero crossings with a high clock frequency and thus ensured for the high-frequency clocking circuit part a voltage situation, which allows a sinusoidal current injection. Since the high-frequency clocking takes place only in a short section of the network period, the advantage of low switching losses is largely retained.
    In one embodiment, the AC voltage is generated by adding the intermediate voltage to the respectively substantially constant reference voltage during the first time interval, and during the second time interval the reference voltage is a non-discontinuous but continuous transition from a first to a second value modulated following the reference voltage.
    In one embodiment, the intermediate voltage is generated by means of a first converter stage from a DC-side DC voltage, and the voltage setpoint for the intermediate voltage is limited upwards to an upper limit, which is an amount below the value of the DC-side DC voltage.
    The distance between the upper limit value and the DC-side DC voltage may be equal to or different from the amount of the lower limit value. Typical values for the distance between the upper limit value and the DC-side DC voltage or the value of the lower limit value are 10% to 30% of the DC-side DC voltage.
    In one embodiment, the control of the first converter stage by means of a multi-loop controla first duty cycle and a first switching signal for a first bridge branch of the first converter stage for generating the intermediate voltage, andfrom a reference value for the reference voltage by dividing this setpoint by the DC-side DC voltage, a second duty cycle and a second switching signal for a second bridge branch of the first converter stage for generating the reference voltage determined.
    The intermediate voltage and the reference voltage result in each case after a filtering by an output filter in the form of a low-pass filter.
    In one embodiment, the voltage setpoint of the intermediate voltage is formed by adding a nominal value of the AC voltage either to the reference value for the reference voltage or to a measured value of the reference voltage.
    If the setpoint is used, the effort for measurement and control becomes smaller. If the current measured value of the reference voltage is used, it is advantageous to suppress deviations of the reference voltage from the nominal value due to the limited dynamics of the low-pass filter.
    In one embodiment, in the first time interval, the setpoint for the reference voltage is different from zero and from a DC-side DC voltage, and the reference voltage is generated from the DC-side DC voltage by a high-frequency clocking of a second bridge branch of the first converter stage.
    In one embodiment, the first converter stage has a first bridge branch and a second bridge branch, and the two bridge branches alternate to produce the substantially constant reference voltage and the sinusoidal half-wave.
    The bridge branches can alternate here after each network period or after several network periods. Thus, a symmetrical thermal load can be achieved.
    In one embodiment, a second bridge branch of the first converter stage in conjunction with a mid-point of the DC-side DC voltage forms a three-point bridge branch to form the reference voltage across an output of the second bridge branch, and is an intermediate DC-side during at least a portion of the second time interval DC voltage connected to the output of the second bridge branch.
    In one embodiment, during the first time interval, the AC voltage is generated by switching the polarity of each successive sinusoidal half-waves of the intermediate voltage, and during the second time interval, the AC voltage by modulating the intermediate voltage by high-frequency switching the polarity of the Intermediate voltage generated.
    This corresponds to a generation of the AC voltage by pulse width modulation.
    In one embodiment, the converter has a first converter stage for generating the intermediate voltage from a DC-side DC voltage and a second converter stage with an output filter for switching the polarity of the intermediate voltage and for forming the AC voltage, wherein by means of a multi-loop control<tb> - <SEP> from a sinusoidal power frequency setpoint or a measured value of the AC voltage, with optional feedforward control of a load current, in a control of the output filter, a setpoint of a local mean value of an output voltage of the second converter stage is determined; and<tb> - <SEP> from this setpoint<tb> <SEP> • <SEP> on the one hand by rectification an absolute value | u2quer * | and from this, after limiting it to the lower limit, determining the voltage reference for the intermediate voltage; and<tb> <SEP> • <SEP> on the other hand, by dividing by the lower limit and limiting the output of the division to values in the interval (+1, -1) a duty cycle is determined, and from the duty cycle, for example by interleaving with +1 and -1 current triangular signal, a pulse width modulated drive signal for switching the second converter stage is determined.
    In one embodiment, the lower limit is varied over time.
    In one embodiment, the duty cycle is not by dividing by the lower limit and limiting the output of the division to values in the interval (+1, -1), but by dividing the setpoint of the local average of the output voltage of the second converter stage by a the interval (+ uC1underline, -uC1underline) limited measured value of the intermediate voltage is formed.
    The device for controlling a single-phase DC / AC converter has an analog and / or digitally operating control unit, which is designed for carrying out the method according to one of the preceding claims.
    The invention will be explained in more detail with reference to possible embodiments, which are illustrated in the accompanying drawings.
    Typographical convention: in the symbols used in the figures, dashes and underscores are u. Like. These are represented in the following text by suffixes such as "across", "underline", etc.<Tb> FIG. 1 <SEP> Power part of a single-stage hybrid modulated single-phase DC / AC full-bridge circuit for bidirectional coupling of a DC source and a single-phase AC network. Further shown: Block diagram of the scheme, wherein the designated for a temporary high frequency clocking part marked by dash-dotted outline and island operation, i. Setting a voltage setpoint u0 * is required on the power supply terminals.<Tb> FIG. 2 <SEP> time characteristic characteristic voltage waveforms of the circuit of FIG. 1; u0 *: setpoint of the mains voltage; uC2 *: curve of the voltage at filter capacitor C2 or the local mean value of the setpoint of the output voltage of bridge branch 2, u2quer *; u2: time characteristic of the output voltage of bridge branch 2; uC1 *: Setpoint of the voltage at capacitor C1 at the output of the low-pass filter (L1C1) of bridge branch 1 (by selecting the course of uC2 *, uC1 * is prevented from falling below a minimum value uC1underline, or farther than uC1underline of the DC Input voltage Ui approaches, so that for the regulation of the current in L1 always a sufficient negative and positive voltage reserve is available). In the interest of a clear presentation, the voltage curves are shown over a network period and additionally stretched in time around a voltage zero crossing.<Tb> FIG. 3 <SEP> Power part of a two-stage hybrid modulated DC / AC full-bridge circuit for the bidirectional coupling of a DC source and a single-phase AC network. Further shown: Block diagram of the scheme, wherein the designated for a temporary high frequency clocking part marked by dash-dotted outline and island operation, i. Setting a voltage setpoint u0 * is required on the power supply terminals.<Tb> <September><Tb> FIG. 4 <SEP> time characteristic characteristic voltage waveforms of the circuit of FIG. 3; u2quer *: setpoint of the local mean value of the voltage at the output of the full bridge; abs (u2quer *): voltage curve resulting from rectification of u2quer *; uC1 *: characteristic of the voltage to be set at capacitor C1 at the output of the low-pass filter (L1C1) of the continuously high-frequency clocked bridge branch; u2 and u2quer: curve of the output voltage of the full bridge and the associated local mean value; uC1underline: value of the limit of uC1 * downwards (ensures sufficient reverse voltage for the regulation of the current in L1). In the interest of a clear presentation, the voltage curves are shown over a network period and additionally stretched in time around a voltage zero crossing.<Tb> FIG. 5 <SEP> Variant of a partial function of the control structure shown in FIG.
    The power section of the single-stage hybrid modulated single-phase DC / AC full-bridge circuit shown in FIG. 1 is characterized by a continuously high-frequency clocked first bridge branch 1 (transistors T11 and T21) and a load only to be formed in the vicinity of the zero crossings. or mains voltage (setpoint u0 *) clocked second bridge branch 2 (transistors T12 and T22) and formed by the outputs of these bridge arms against the negative rail of the DC supply voltage Ui low-pass filter L1C1 and L2C2. The load, represented by a resistor R, is applied to the sine voltage u0 appearing between the outputs of the two low-pass filters. To power the system, a DC source Ui is arranged between the positive voltage rail and negative voltage rail, the two bridge branches 1 and 2 are. The low-pass filter L2C2 can be omitted for a modulation according to the prior art, since there the second bridge branch 2 is switched only at mains frequency, i. has no pulse width modulation; Usually, however, an EMC filter, not shown in FIG. 1, is to be inserted into the lines leading to the load in order to limit the conducted interference emission of the system to permissible values.
    To form the desired sinusoidal output voltage u0 *, a corresponding difference in the voltages of the two filter capacitors C1 and C2, ie uC1 and uC2, must be set, i. voltage setpoints uC1 * and uC2 * must be specified for both capacitors. The setpoint uC1 * can therefore be formed by adding the sinusoidal setpoint value u0 * of the AC output voltage to be formed and a setpoint value uC2 *, wherein the course of uC2 * is selected such that uC1 * always remains greater than a minimum value uC1underline, or only as far as the level Ui approaches the DC input voltage that remains a difference in the amount of uC1underline. This is e.g. by the trapezoidal shape of uC2 * shown in FIG. 2, advantageously the minimum value of uC2 * being equal to zero and the maximum value being equal to Ui, since then for generating uC2 = uC2 * at C2 only within the edges of the trapezoidal profile, Thus, during the transition from zero to Ui and vice versa, a clocking of the second bridge branch 2 is required. Within the horizontal sections of u2 *, the bridge branch remains clamped to the positive or negative DC voltage rail, thus eliminating switching losses in T12 and T22. Since μC1 * always maintains a distance uC1underline down from zero and the distance uC1underline upwards from Ui, a minimum voltage reserve for the build-up or reduction of the current in L1 is ensured within the entire network period; If e.g. T11 is switched by bridge branch 1, then comes to lie at least u1underline L1, whereby a correspondingly rapid current build-up can take place; on the other hand, when T21 is turned on, it is at least negatively negative across L1 and a rapid current reduction is ensured. This minimum voltage reserve is also advantageous for circuits operating at the boundary of continuous and discontinuous current conduction (Boundary Conduction Mode, BCM, or Resonant Transition Mode or Triangular Current Mode, TCM) with a characteristic triangular course of the current in L1, since then the variation of the current Restricted switching frequency or the conducted interference can be kept at higher frequencies, whereby the kink frequency of the network-side EMC filter selected higher or its size can be reduced.
    The determination of uC2 * according to the above description can be done by a digitally or analog realized control unit based on measurements of one or more voltage or current measurements (not shown in the figures). For example, a known control unit which generates signals for switching the second bridge branch 2 may be modified to generate the trapezoidal shape of uC2 * or another continuous course between the upper and lower constant values.
    The voltage across capacitor C1 is set to the desired voltage value uC1 * by means of a multi-loop control with a feedforward control based in part on the state of the art on the basis of signals corresponding to the load current i0 and the voltage setpoint uC1 * of the output voltage, wherein the switching signal sl for the Control of the two transistors T11 and T21 results. The adjustment of uC2 * is advantageously carried out directly in a controlled manner with little implementation effort, i. it is determined by dividing uC2 * by Ui the duty D2 of the second bridge branch 2 and then in a known form by intersection with a triangle signal d2 (comparator K2) receive the pulse width modulated switching signal s2 for driving the second bridge branch 2. The corresponding pulse width modulated output voltage of the second bridge branch 2 is then converted by means of low-pass filtering (L2C2) into the desired output voltage uc2 *.
    Alternatively to the addition of u0 * and uC2 *, the formation of uC1 * can also be effected by adding u0 * and the current voltage uC2, which advantageously suppresses deviations from uC2 * and uC2 due to the limited dynamics of the low-pass filter L2C2.
    If a continuous high-frequency clocking of the second bridge branch 2 can be accepted over the entire network period when using fast-switching transistors, the voltage level of the horizontal sections of uC2 * in FIG. 2 can also be different from zero and Ui and replaced by a general time function ie be selected variable in time, but always make sure that the resulting voltage uC1 * in any case within the absolute limits Ui and zero remains, or advantageously a sufficient difference (voltage reserve of the current control) over these limits.
    Further, in symmetric execution of, the voltages uC1 * and uC2 * einprägenden regulations (it is then the same as for uC1 * for uC2 * an explicit regulation - and not just a controller - provide) the function of the two bridge arms 1 and 2 alternate, ie the continuously clocking bridge branch generate the trapezoidal current profile in every second line half-wave (and vice versa), which advantageously results in symmetrical thermal loading of the bridge branch.
    Finally, it is possible to dispense with a temporary clocking or pulse width modulation of the second bridge branch 2 and instead a low-frequency three-point modulation be made. For this purpose, the second bridge branch 2 is to be expanded by a further bidirectional switch T3Mp from the bridge branch output to a midpoint of the DC input voltage (T-type structure; alternatively, other forms of three-point bridge branches, eg a structure known as a neutral-point-clamped topology, can be used ). The bridge branch then has three-point characteristics, i. it can be generated by appropriate control of T11, T21 and T3Mp at the output of the bridge branch opposite the negative DC voltage rail, the voltage levels zero, Ui / 2 and Ui. Advantageously, the trapezoid voltage u2 * is then approximated such that T3Mp is switched through within the edge times, during the transition from zero to Ui and vice versa, while T11 and T21 block. Advantageously, because of the low-frequency clocking, the low-pass filter L2C2 can be omitted or have a smaller size.
    Also, the continuously clocked bridge branch 1 can then be performed in three-point form, whereby the above-mentioned alternation of the clocked and clamped bridge branch is possible and due to the lower Stromrippeis the low-pass filter L1C1 can be reduced.
    In Fig. 3, in the basic structure of single-phase PFC rectifier circuits known circuit topology of the power part of a two-stage hybrid modulated single-phase DC / AC converter is shown, which, powered by a DC voltage source Ui buck converter circuit (bridge branch with transistors T + and T- with anti-parallel diodes D + and D- and one of the bridge branch output against the negative DC voltage rail laid low-pass filter L1C1) and a downstream, fed from the filter capacitor C1 transistor full bridge circuit with AC-side low-pass filter L2C2, which by a resistor R load shown across the filter capacitor C2, the voltage is guided by appropriate control sinusoidal power frequency. For conventional modulation of the circuit, the transistor full bridge is switched only at the mains frequency, which means that the filter L2C2 can also be omitted, and the load voltage or AC voltage is defined directly via uC1. The voltage uC1 then has the course of a rectified sine voltage, which is converted by appropriate switching of the full bridge in an AC voltage (inversion of every second half-wave). For the regulation of the system then, as shown in FIG. 1, in addition to the power-frequency control of the full bridge, also a typically multi-loop control of uC1 (regulation of uC1 with subordinate current regulation, ie regulation of iL1 and downstream pulse width modulation for controlling T + and T-). , as well as corresponding pilot control, for example of the current i at the output of C1).
    It is the specification of the setpoint uC1 * made so that uC1 always greater than a minimum value uC1underline remains, so that for the control of iL1 always a sufficient voltage reserve remains. If iL1 is to be e.g. can then be broken down, and thus in any case at least uC1underline in the negative direction, i. in the direction of degradation of i1 acting on L1. In order to still obtain the desired sinusoidal profile of the load voltage uC2, however, the transistor full bridge with corresponding pulse width modulation must then be operated within the intervals where uC1 remains clamped on uC1underline. Furthermore, a low-pass filter L2C2 must be arranged at the output of the transistor full bridge in order to ensure a smooth progression of the load voltage.
    In a conventional manner can now starting from the sinusoidal, mains frequency setpoint u0 * the load voltage by a zweischleifige control of the output filter (control of uC2 and secondary control of iL2, advantageously with feedforward control of the load current i0) u0quer with u0 * piloted setpoint u2quer * of the local mean of the full-bridge output voltage. This can then be converted into magnitude (u2verse *) by rectification and, after limiting it to uC1underline, downwards the desired value uC1 * can be obtained. Further, u2equ * is divided by u1, to compute the required duty cycle D2 of the full transistor bridge (e.g., simply controlled to always turn on diagonally opposite transistors - bipolar modulation). However, this calculation does not yield meaningful for u2quer *> uC1underline. values outside the range (+1, 1), therefore a corresponding limitation of the output of the division to values in the range (+1, -1) is required. The thus calculated duty cycle D2 is blended in a conventional manner with a triangle signal d2 running between +1 and -1 (comparator K2), thus obtaining the pulse width modulated drive signal s2 for the transistor full bridge. It then remains advantageous, if u2 transverse * over uC1underline or below -uC1underline, the duty cycle D2 is clamped to the value +1 or -1, and the voltage uC1 is forwarded in the correct polarity to the output of the full bridge or ultimately a sinusoidal load voltage is formed ( see Fig. 4).
    Another advantage is the back translation of the current iL2 through the full bridge at the DC input, i. into a corresponding current i for a precontrol of the setpoint iL1 * to be formed by the regulation of iL1. The local mean value iquer of i can be determined by multiplication of iL2 by D2 and in this form can be used directly as a precontrol signal of iL1.
    It may also have a temporal variation uc1underline, which may be e.g. in Boundary Mode Control (BCM) of the buck converter T +, T-, L1C1 (can also be performed by several phases offset clocked stages with only temporary timing, ie continuous or temporary clamping of one or more bridge branches) is advantageously chosen so that the switching frequency varies over time and on the one hand remains at high values and on the other hand reduces the amplitudes of the interference emission at individual frequencies, or the interference emission is distributed over a wider frequency range.
    It should also be emphasized that the low-pass filter L1C1 or L2C2 may be designed in multiple stages if necessary.
    Finally, for the calculation of the duty cycle instead of uC1underline within the interval where a pulse width modulation of the transistor full bridge occurs also the actual course of uC1 be used. Deviations from uC1 from the setpoint uC1underline for the formation of u2 are thus taken directly into account. For the division of u2 * then the voltage uC1 limited to the interval (+ uC1underline, -uC1underline) is used instead of uC1underline (FIG. 5).
    Finally, it should be pointed out that the concepts described above for single-mode operation and two-stage hybrid-modulated inverter circuits can also be used analogously for the coupling of the inverter circuits to a predetermined mains voltage. Only the voltage setpoint u0 * must then be replaced by the measured value u0 or, for the definition of the output of the full bridge with the two bridge branches 1 and 2, a nominal value of the current to be supplied to the grid (corresponding to the setpoint value iL1 * of the subordinate current control or specify the two-stage system the setpoint iL2 *) accordingly.
    Further, it should be emphasized that, after the concepts described above are independent of the phase relationship of line current and line voltage, in particular also for rectifier operation (e.g., single phase PFC rectification), i. Power supply of a DC voltage source from the AC grid can apply.
    权利要求:
    Claims (13)
    [1]
    1. A method for controlling a single-phase DC / AC converter, wherein in the operation of the converter, an electric power from a DC (DC) side to an AC side (AC) or vice versa is transmitted and thereby in successive vibrations one with a Fundamental frequency on the AC side occurring sinusoidally extending AC voltage (u0) each during a first time interval of the half-oscillation, which extends over a substantial range of half-oscillation, a first converter stage (1, 2, 3) an intermediate voltage (uC1) with a generated sinusoidal half-wave, and the AC voltage (u0)- is generated by adding the intermediate voltage (uC1) to a respectively during the first time interval substantially constant reference voltage (uC2), orIs generated by switching the polarity of each successive sinusoidal half oscillations of the intermediate voltage (uC1),characterized in that in each case during a second time interval, which has no overlap with the first time interval, a voltage setpoint (uC1 *) for the intermediate voltage (uC1) is limited down to a lower limit (uC1underline).
    [2]
    2. The method according to claim 1, wherein the AC voltage (u0) is generated by adding the intermediate voltage (uC1) to the respectively during the first time interval substantially constant reference voltage (uC2), and during the second time interval, the reference voltage (uC2) one is not modulated following a sudden but continuous transition from a first to a second value of the reference voltage (uC2).
    [3]
    3. The method according to claim 2, wherein the intermediate voltage (uC1) by means of a first converter stage (1, 2) from a DC-side DC voltage (Ui) is generated, and the voltage setpoint (uC1 *) for the intermediate voltage (uC1) upwards is limited by an amount (uC1underline) below the value of the DC-side DC voltage (Ui).
    [4]
    4. The method according to claim 3, wherein for the control of the first converter stage (1, 2) by means of a multi-loop controlFrom a voltage setpoint (uC1 *) of the intermediate voltage (uC1), with optional feedforward control of a load current (i0) and / or the output voltage (uC1), a first duty cycle (D1) and a first switching signal (s1) for a first bridge branch (1 ) of the first converter stage (1, 2) for generating the intermediate voltage (uC1), andA second duty cycle (D2) and a second switching signal (s2) for a second bridge branch (2) from a reference value (uC2 *) for the reference voltage (uC2) by dividing this reference value (uC2 *) by the DC-side DC voltage (Ui) ) of the first converter stage (1, 2) for generating the reference voltage (uC2) is determined.
    [5]
    5. The method according to claim 4, wherein the voltage setpoint (uC1 *) of the intermediate voltage (uC1) by adding a desired value (u0 *) of the AC voltage (u0) either to the setpoint (uC2 *) for the reference voltage (uC2) or to a Measured value of the reference voltage (uC2) is formed.
    [6]
    6. The method according to any one of claims 2 to 5, wherein in the first time interval, the reference value (uC2 *) for the reference voltage (uC2) is different from zero and from a DC-side DC voltage (Ui), and the reference voltage (uC2) from the DC-side DC voltage (Ui) by a high-frequency clocking of a second bridge branch (2) of the first converter stage (1, 2) is generated.
    [7]
    7. The method according to any one of claims 2 to 6, wherein the first converter stage (1, 2) has a first bridge branch (1) and a second bridge branch (2), and the two bridge branches (1, 2) for generating the substantially alternate constant reference voltage and the sinusoidal half-wave.
    [8]
    8. Method according to one of claims 2 to 7, wherein a second bridge branch (2) of the first converter stage (1, 2) in conjunction with a midpoint of the DC-side DC voltage (Ui) a three-point bridge branch to form the reference voltage (uC2) via a Output of the second bridge branch (2), and during at least part of the second time interval, an average DC-side DC voltage to the output of the second bridge branch (2) is connected.
    [9]
    9. The method according to claim 1, wherein during the first time interval, the AC voltage (u0) is generated by switching the polarity of each successive sinusoidal oscillations of the intermediate voltage (uC1 *), and during the second time interval, the AC voltage (u0 ) is generated by modulation of the intermediate voltage (uC1 *) by high-frequency switching of the polarity of the intermediate voltage (uC1 *).
    [10]
    10. The method according to claim 9, wherein the converter comprises a first converter stage (3) for generating the intermediate voltage (uC1) from a DC-side DC voltage (Ui) and a second converter stage (4) with an output filter (L2, C2) for switching the Polarity of the intermediate voltage (uC1) and to the formation of the AC voltage (u0), by means of a multi-loop control- from a sinusoidal mains frequency setpoint (u0 *) or a measured value (u0) of the AC voltage, with optional feedforward control of a load current (i0), in a control of the output filter, a setpoint value (u2quer *) of a local mean value of an output voltage (u2) the second converter stage (4) is determined; and- from this setpoint (u2quer *)• on the one hand, by rectification, an absolute value | u2quer * | and from this, after limiting it to the lower limit (uC1underline), determining the voltage setpoint (uC1 *) for the intermediate voltage (uC1); and• On the other hand, by dividing by the lower limit (uC1underline) and limiting the output of the division to values in the interval (+1, -1) a duty cycle (D2) is determined, and from the duty cycle (D2), for example by interleaving with an intermediate +1 and -1 current triangular signal (d2), a pulse width modulated drive signal (s2) for switching the second converter stage (4) is determined.
    [11]
    11. The method according to claim 9 or 10, wherein the lower limit (μC1underline) varies over time.
    [12]
    12. The method according to claim 9 or 10, wherein the duty cycle (D2) not by dividing by the lower limit (uC1underline) and limiting the output of the division to values in the interval (+1, -1), but by dividing the setpoint (u2quer *) of the local mean value of the output voltage (u2) of the second converter stage (4) is formed by a measured value of the intermediate voltage (uC1) limited to the interval (+ uC1underline, -uC1underline).
    [13]
    13. An apparatus for controlling a single-phase DC / AC converter, comprising an analog and / or digitally operating control unit, which is designed for carrying out the method according to one of the preceding claims.
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    同族专利:
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    CH711423B1|2019-07-31|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2018-11-15| PCAR| Change of the address of the representative|Free format text: NEW ADDRESS: POSTFACH, 8032 ZUERICH (CH) |
    2021-03-31| PL| Patent ceased|
    优先权:
    申请号 | 申请日 | 专利标题
    CH01139/15A|CH711423B1|2015-08-06|2015-08-06|Method and device for controlling a single-phase DC / AC converter.|CH01139/15A| CH711423B1|2015-08-06|2015-08-06|Method and device for controlling a single-phase DC / AC converter.|
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